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/ MacHack 1996 / MacHack 1996.toast / Hacks / Hacks ’92 / RISCy Bitsness / cpu1.v < prev    next >
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Verilog source code  |  1992-06-18  |  2.5 KB  |  170 lines  |  [TEXT/MPS ]
  1. /*
  2. 10     29        28-24    23-19 18-0
  3. 00    0/1 l/s     r        r      abs - sext
  4.  
  5.     load        r, n(r)
  6.     store        r, n(r)
  7.  
  8. 10     29,18-15    28-24    23-19     14-0/4-0
  9. 01    type        r        r         v/r
  10.  
  11.     add        r, r, r/v
  12.     sub         r, r, r/v
  13.     and        r, r, r/v
  14.     or        r, r, r/v
  15.     xor        r, r, r/v
  16.     lt        r, r, r/v
  17.     le        r, r, r/v
  18.     eq        r, r, r/v
  19.     lsh        r, r, r/v
  20.     jmp        r, r, r/v
  21.     halt        r, r, r/v
  22.  
  23. 10     29             28-24    23-0
  24. 10    0/1 t/f      r        abs
  25.         
  26.     bt        r, abs
  27.     bf        r, abs
  28.  
  29. 10     29             28-24    23-0/15-0
  30. 11    0/1 /h      r        v
  31.  
  32.     const    r, v        23-0
  33.     consth    r, v        15-0
  34.  
  35.  
  36.  
  37. bus:
  38.     clock
  39.     reset
  40.     a31_2
  41.     d31_0
  42.     r/w
  43.     start
  44.     ack
  45.     near
  46. */
  47.     
  48. module cpu1(clock, reset, a, d, rw, start, ack);
  49.  
  50.     input            clock;
  51.     input            reset;
  52.     
  53.     inout     [31: 0]d;
  54.     reg         [31: 0]dd;
  55.     assign        d = dd;
  56.     
  57.     output     [31: 0]a;
  58.     reg         [31: 0]a;
  59.     
  60.     output            rw;
  61.     reg                rw;
  62.     
  63.     output            start;
  64.     reg                start;
  65.     
  66.     output            near;
  67.     reg                near;
  68.     
  69.     input            ack;
  70.     
  71.     reg         [31: 0]r[32];
  72.     
  73.     reg         [31: 0]pc, b, c, res, next, i, tmp;
  74.     reg         [ 4: 0]rr;
  75.     reg                br;
  76.     
  77.     always @(negedge clock) 
  78.     if (~reset) begin
  79.         pc = 0;
  80.         start = 1;
  81.         near = 0;
  82.         r[0] = 0;
  83.         br = 0;
  84.         rr = 0;
  85.     end else begin
  86.         a = pc;
  87.         start = 0;
  88.         if (br) begin
  89.             br = 0;
  90.             pc = next;
  91.         end else begin
  92.             pc = pc + 4;
  93.         end
  94.         rw = 1;
  95.         dd = 32'bz;
  96.         @(negedge clock);
  97.         while (ack)
  98.             @(negedge clock);
  99.         start = 1;
  100.         i = d;
  101.         @(negedge clock);
  102.         case (i[31:30]) 
  103.         0:    begin
  104.                 a = r[i[28:24]]+i[18:0];
  105.                 if (~i[29]) begin
  106.                     rw = 1;
  107.                     rr = i[23:19];
  108.                     dd = 32'bz;
  109.                 end else begin
  110.                     rw = 0;
  111.                     dd = r[i[23:19]];
  112.                     rr = 0;
  113.                 end
  114.                 start = 0;
  115.                 @(negedge clock);
  116.                 while (ack)
  117.                     @(negedge clock);
  118.                 start = 1;
  119.                 res = d;
  120.             end
  121.         1:    begin
  122.                 rr = i[28:24];
  123.                 b = r[i[23:19]];
  124.                 if (i[29]) begin
  125.                     c = {17'b0,i[14:0]};
  126.                 end else begin
  127.                     c = r[i[4:0]];
  128.                 end
  129.                 case (i[18:15])
  130.                 0:    res = b + c;
  131.                 1:    res = b - c;
  132.                 2:    res = b&c;
  133.                 3:    res = b|c;
  134.                 4:    res = b^c;
  135.                 5:    res = (b < c ? 32'h80000000:32'0);
  136.                 6:    res = (b <= c ? 32'h80000000:32'0);
  137.                 7:    res = (b == c ? 32'h80000000:32'0);
  138.                 8:    res = (c[31]?b<<c:b>>(-c));
  139.                 9:    begin
  140.                         res = pc;
  141.                         br = 1;
  142.                         next = b + c;
  143.                     end
  144.                 10:    begin
  145.                         #100
  146.                         $stop;
  147.                     end
  148.                 endcase
  149.             end
  150.         2:    begin
  151.                 next = {8'b0,i[23:0]};
  152.                 rr = 0;
  153.                 tmp = r[i[28:24]];
  154.                 br = i[29]^tmp[31];
  155.             end
  156.         3:    begin
  157.                 rr = i[28:24];
  158.                 if (i[29]) begin
  159.                     tmp = r[i[28:24]];
  160.                     res = {i[15:0],tmp[15:0]};
  161.                 end else begin
  162.                     res = {8'b0,i[23:0]};
  163.                 end
  164.             end
  165.         endcase
  166.         if (rr != 0)
  167.             r[rr] = res;
  168.     end
  169.  
  170. endmodule